1. Field of the Invention
The present invention relates to a method of performing threshold voltage adjustment for MOS transistors, more particularly, to a method of forming a MOS transistor with precise and stable threshold voltage.
2. Description of the Prior Art
Integrated Circuit (IC) technology has produced dramatic advances over the past 20 years. The increasing of the semiconductor device's integration necessitates the shrinkage of the critical dimension of the MOS devices. With further shrinking of dimensions, the circuit processes become more stringent; old requirements are tightened, and new requirements have to be considered. In order for obtaining absolute isolation, threshold voltage for the field-oxide areas must be higher to isolate individual devices. The localized oxidation isolation method (LOCOS) was the most dominant isolation process used in IC technologies in the past. However, it is quietly difficult to reduce the bird's beak length to much less than 0.1 um per side with totally flat topology. Therefore, for sub-quarter-micronmeter technology, a new approach to isolation with totally flat topology was recently disclosed, i.e. shallow trench isolation (STI).
A paper "A New Trench Isolation Technology as a Replacement of LOCOS" was disclosed in IEDM Tech. Dig., 578(1984) by H. Mikoshiba et al. Referring now to FIG. 1, a cross-sectional diagram of a shallow trench isolation on the basis of the prior art is shown. Firstly, trenches about 0.3 to 0.8 um deep are anisotropically etched into the silicon substrate 10 through dry etching (only one trench is shown in the Figure). Active regions are those that are protected from the etch when the trenches are created. A thermal oxidation process is performed to form an oxide layer 60, so as to anneal the damaged sidewall of the shallow trenches. Next, a CVD oxide layer is deposited on the wafer surface and then etched back to form the shallow trench isolations 80 so that it remains only in the recesses, with its top surface at the same level as the original silicon surface. Etchback is performed using a sacrificial photoresist method, or a CMP (Chemical Mechanical Polishing) process. After the formation of shallow trench isolations 80, active devices are going to be fabricated. CMOS circuits require a balanced pair of n- and p-channel enhancement mode devices (hereinafter NMOS and PMOS) on the same chip. In order to obtain matched complementary devices, ion implantation processes for threshold voltage adjustment of NMOSs and PMOSs are needed.
As shown in FIG. 1, there is a silicon/silicon dioxide interface between the shallow trench isolations and the active regions. Though a thermal oxidation process is performed during the STI formation process, there are unavoidably lots of defects existing on the interface. There are still many thermal steps in the subsequent process, so that the doped impurities (P- or N-type) for threshold voltage adjustment diffuse along the interface toward the bottom of the shallow trenches. The arrow in FIG. 1 shows the diffusing direction. As a result, the doping concentration for threshold voltage adjustment loses during the thermal steps. Consequently, the final threshold voltage of each PMOS or NMOS is different from the original design. This variation of threshold voltage results in poor yield and bad reliability.